1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a shallow impurity layer.
2. Description of the Related Art
In recent years, electric circuits consisting of a large number of transistors and resisters are arranged in the main portion of a computer or communication equipment, and a large scale integrated circuit (LSI) obtained by integrating the large number of transistors and resistors in one chip is frequently used as the electric circuit. The improvement of the performance of one LSI is important to design high-performance equipment. Since this improvement can be achieved by increasing a degree of integration of, e.g., an LSI, a field effect transistor (FET) must be micro-patterned. For this purpose, when the length of each gate of the FET is decreased, source and drain regions must be shallow. For example, low-acceleration ion implantation is popularly used for forming these regions. In this method, shallow source and drain regions each having a depth of about 0.1 .mu.m can be formed, and a micro-patterned FET having high performance can be formed.
However, an impurity layer formed by only the ion implantation has a high resistance, i.e., a sheet resistance of 100.OMEGA./.quadrature. or more. In order to increase the speed of the FET, the sheet resistance of the impurity layer must be decreased to cause a drain current to properly flow.
When the diameter of a contact hole is decreased, Si contained in an A.lambda.-Si-Cu alloy used as an electrode wiring material is precipitated in the contact hole to cause an increase in contact resistivity.
In order to solve the above two problems, a method of metallizing a part of the impurity layer or the inside of the contact hole is considered. For example, a method called silicide is used.
According to this method, after a field oxide film 83 is formed on a (100) Si substrate 81, a gate oxide film 85, a gate electrode 87, and a gate side-wall insulating film 89 (thickness of about 150 nm) are formed on the field oxide film 83. An impurity diffusion layer 91 is formed in the surface of the Si substrate 81 by well-known ion implantation, and a titanium (Ti) film 93 is deposited on the entire surface of the resultant structure to have a thickness of 40 nm.
As shown in FIG. 1B, the surface of the Si substrate 81 is heated by lamp annealing, a silicide film, i.e., a titanium silicide (TiSi.sub.2) film 9, is formed in the surface layer of the impurity diffusion layer 91.
As shown in FIG. 1C, after the non-reacted Ti film 93 is removed by etching, an insulating film 97 is formed. Finally, contact holes are formed in the insulating film 97, and electrode wiring layers 99 are formed, thereby obtaining an FET.
According to this method, the TiSi.sub.2 film 95 having a thickness of 80 nm can be formed, and the sheet resistance can be decreased to about 2 to 3.OMEGA./.quadrature..
However, recent extensive studies have pointed out the following problems of a method of this type.
The depth of a diffusion layer must be set to be 0.1 .mu.m or less to form an FET having a gate length of 0.3 .mu.m or less. Boron (B) used for forming a p.sup.+ -type diffusion layer has a diffusion coefficient smaller than that of arsenic (As) used for forming an n.sup.+ -type diffusion layer. For this reason, in order to form such a shallow p.sup.+ -type diffusion layer by using B, annealing must be performed at a low temperature of about 850.degree. C.
When the TiSi.sub.2 film 95 is formed by the above method, however, B ions in a high-concentration region formed on the surface of the Si substrate are consumed for forming the TiSi.sub.2 film 95. It is found that the B concentration of a TiSi.sub.2 /Si interface is considerably decreased.
For example, when the p.sup.+ -type diffusion layer is formed by annealing at 850.degree. C using ion implantation of BF.sub.2, the B concentration of the TiSi.sub.2 /Si interface is a low value, i.e., 3.times.10.sup.19 cm.sup.-3 or less. On the other hand, high-temperature annealing in a POC.lambda..sub.3 gas atmosphere at 850.degree. C. for 60 minutes may be performed to
the reliability of the element after the TiSi.sub.2 film is formed. However, in this case, the B concentration of the TiSi.sub.2 /Si interface is further decreased. As a result, the contact resistivity of the electrode wiring layer to the p.sup.+ -type diffusion layer is very large value, i.e., 1.times.10.sup.14 .OMEGA..multidot.cm.sup.2 or more, ohmic and electric connection cannot be obtained between the p.sup.+ -type diffusion layer and the electrode wiring layer.
As a countermeasure against the above problem, the following attempt is made. That is, after the TiSi.sub.2 film 95 is formed, B or BF.sub.2 ions are implanted near the TiSi.sub.2 /Si interface from the upper surface of the TiSi.sub.2 film 95, and the resultant structure is annealed in a nitrogen atmosphere to increase the B concentration of the TiSi.sub.2 /Si interface.
However, B ions must be implanted at a high acceleration voltage of 30 keV or more to use this method, and a p.sup.+ -type diffusion layer is deeply formed under the TiSi.sub.2 film 95. For this reason, the method cannot be applied to a micro-patterned device requiring a shallow junction, and Ti ions in the TiSi.sub.2 film 95 are knocked in the Si substrate 81 by performing the ion implantation at a high acceleration voltage, i.e., a knock-on phenomenon occurs. Therefore, defects are formed in the diffusion layer and junction leakage is increased, resulting in inconvenience.
When a wiring layer obtained by stacking a metal compound layer such as a TiSi.sub.2 layer on a polysilicon layer containing an impurity such as B is to be formed, since the impurity is consumed, the wiring resistance of the polysilicon layer is increased.
On the other hand, the salicide method is also applied to a complementary MOS (CMOS)-FET. That is, in this case, the complementary CMOS-FET is manufactured by the step shown in FIG. 12 except for formation of p.sup.+ -and n.sup.+ -type impurity diffusion layers in the surface layer of the Si substrate 81. In this case, since the contact resistivity of the electrode wiring layer to the p.sup.+ -type diffusion layer has a very large value, i.e., 1.times.10.sup.-4 .OMEGA..multidot.cm.sup.2 or more, ohmic and electric connection cannot be obtained between the p.sup.+ -type diffusion layer and the electrode wiring layer.
In order to solve this problem, the following semiconductor device is proposed. In this semiconductor device, metal silicide films of different types are formed on the p.sup.+ -type diffusion layer and the n.sup.+ -type diffusion layer of the CMOS-FET, respectively. For example, a platinum silicide film is formed on the p.sup.+ -type diffusion layer and a Ti silicide film is formed on the n.sup.+ -type diffusion layer. However, since the number of steps in manufacturing the semiconductor device is very large, an inexpensive high-performance CMOS-FET cannot be obtained.
As described above, when the shallow p.sup.+ -type diffusion layer having a thickness of 0.1 .mu.m or less is formed, in a conventional salicide method, an impurity concentration of the interface between a TiSi.sub.2 film and a p.sup.+ -type diffusion layer is decreased in proportion to an increase in time for high-temperature annealing. For this reason, a contact resistivity is increased, and it is difficult to properly perform electric connection between the p.sup.+ -type diffusion layer and an electrode wiring layer. In addition, when an impurity is doped in the interface between the p.sup.+ -type diffusion layer and the Si substrate by ion implantation, the following new problems are posed. That is, the depth of junction is increased, and at the same time, junction leakage is increased.
In addition, the resistance is disadvantageously increased by consuming an impurity even in a stacked wiring layer consisting of a polysilicon film and a TiSi.sub.2 film.